The present invention relates to the field of static random access memory (SRAM) arrays, and to a SRAM memory architecture providing for bit line partitioning.
FIG. 1 shows a SRAM memory array architecture of the prior art. This architecture utilizes a six transistor memory cell 200 as shown in FIG. 2. The six transistor SRAM bit cell 200 shown in FIG. 2 utilizes a first supply voltage, VDD 217, and a ground connection 218. The cell also includes a word line WLC. Bit lines BTC and BBC provide a connection to read and write data to the cell. The bit cell also includes a storage cell which includes four transistors, 206, 208, 210, 212, configured to store data. As is known in the art, transistors 206 and 208 act as load transistors and transistors 210 and 212 act as cross coupled storage transistors. As shown in the bit cell 200, the load transistors 206 and 208 are PMOS transistors, and storage transistors 210 and 212 are NMOS transistors. NMOS Transistors 214 and 216 arc word line, or row select, pass transistors.
In a static mode, when the cells in the memory array are not in write or read mode, bit lines BTC and BBC, shown in FIG. 2, are precharged to a VDD level, and the word line shown in FIG. 2 as WLC is at logic zero. In this static state, a programmed cell can maintain the information equivalent to logic 0 or logic 1, since n-channel devices 214 and 216 are off, which isolates the storage cell that includes devices 206, 208, 210 and 212.
In a write mode, the WLC line (e.g. WL0, WL1 . . . WLN) which is coupled to a row of cells (e.g. N00, N01 . . . N0M), as shown in FIG. 1, which contains the cell being written to, is driven to logic 1 or VDD to turn on (open) the pass transistors, thereby providing access to the storage cell. To write to the cell to be programmed to store a binary 1, the bit line BTC for the cell being written to is driven to logic 1, and the bit line BBC is driven to logic 0. This results in the cell being programmed to logic 1, where the voltage at node 202 will be set at logic 1 and the voltage at node 204 will be set at logic 0 as is known in the art. To program the cell to logic 0 the bit line BTC is driven to logic 0 and the bit line BBC is driven to logic 1, such that 202 will be set at logic 0 and 204 will be set at logic 1 as is known in the art.
In the static mode, in between read and write operations, the bit lines BTC and BBC are held at a precharge voltage VDD using the PMOS transistors 102 of the precharge circuit 106 shown in FIG. 1. In the static mode the word line (WL0, WL1, . . . WLN) pass transistors 214 and 216 shown in FIG. 2 are held closed as the WLC voltage is at logic zero.
To read the data from the cell the WLC voltage is changed to logic 1. The signal of voltage logic 1 on WLC is applied to the gates of the word line pass transistors 214 and 216, which opens the word line pass transistors 214 and 216, so that current can flow through the transistors. In addition to the WLC voltage being set to logic 1, the precharge circuit 106 is closed so that the bit lines BTC and BBC are allowed to float. With the word line pass gate transistors open, one of the bit lines BTC and BBC will discharge depending on which node 202 or 204 is at zero. For example, if the cell is programmed at logic 0 then the BTC bit line will discharge through the NMOS transistor 214 and the cross coupled storage transistor 210, and BBC would remain floating at the VDD level. If the cell was programmed at logic 1 then BBC would discharge through 216 and 212, and BTC would remain at VDD. The switch (SW0, SW1 . . . SWM) connected to the cell which is being read will be closed (conductive) and the sense circuitry 104 will read the difference in voltage in the bit lines BTC and BBC to determine whether the data is 1 (one) or 0 (zero).
In the prior art Static Random Access (SRAM) memory architecture 100 as shown in FIG. 1, there are three stages of operation. At stage 1 memory read/write operations require that all bit lines (BT0, BB0, BT1, BB1, . . . BTM, BBM) be precharged to logic 1 by the precharge circuitry 106, the precharge circuitry provides PMOS transistors 102, which in the static mode are opened by a PRCHG voltage signal 108 being at logic 0, which is applied to the gates of the PMOS transistors 102. Also all word lines (WL0, WL1 . . . WLN) are set to logic 0 before read read/write operation for any cell occurs.
At stage 2 of the memory read/write mode all are of the PMOS transistors 102 are closed (PRCHG voltage 108 is set to logic 1), so that the voltage on the bit lines is allowed to float, instead of being held at VDD. One of the word lines (e.g. WL0) is driven to logic 1 All the 6T (6-transistor)core memory cells (e.g. bit cells N00, N01 . . . N0M) coupled to this word line begin to discharge the bit lines (e.g. BT0, BB, BT1, BB1 . . . BTM, BBM). The discharge of the bit lines at this stage causes a large active AC power dissipation.
Stage 3 of the memory bit cell read/write operation is selecting one of the switches (SW0, SW1 . . . SWM) in the MUX block 103 by setting Y0, Y1 . . . or YM to logic 1. As shown in FIG. 1, Y0 is selecting column 1. To write data to a bit cell at this stage requires using a write circuit 104 to program the selected individual bit cell, by applying a voltage differential to bit lines BT0 and BB0. (The write circuitry and sense circuitry is known to one of skill in the art, and shown as block 104 in FIG. 1.) To read data from the bit cell requires amplifying the differential signal between the bit lines BTC and BBC using a sense amplifier and then routing this to an output circuit.
Regardless of which mode is used, whether read or write, a bit line for each column of SRAM memory bit cells of the complete array will be discharged during every read/write operation, and before a new read/write cycle can begin, and the array has to precharged again. This is because the same PRCHG signal is applied to the gates of all of the PMOS transistors 102 of the precharge circuit 106, and all of the bit cells coupled to word line with logic 1 have word line pass transistors (e.g., 214 and 216) which are opened as a result of the word line generating a logic 1 signal. Stated another way, all the bit lines have to precharged again because all have been discharged during the read/write operation.
One problem with this prior approach is that, for each read/write cycle, enough power to precharge and discharge all of the bit line pairs in the array is consumed, while all that is really needed is to program or read information for one bit line pair (e.g. BTC and BBC) during each read or write cycle.
As disclosed in the patent application filed on Apr. 9, 2002, entitled LOW POWER STATIC RAM ARCHITECTURE (U.S. application Ser. No. 10/119,191) which has common inventors to the present application, and is assigned to the National Semiconductor Corporation, the assignee of the present application, one approach to reduce the power consumed during each read write cycle is to implement an 8 bit memory cell where a column select signal can be used in conjunction with the a word select signal to limit the power discharge during each cycle to a particular column. The U.S. application Ser. No. 10/119,191 referred to above is hereby incorporated by reference in its entirety. As further discussed in the pending patent application Ser. No. 10/215,678 filed on Aug. 10, 2002, entitled LOW AC POWER STATIC RAM ARCHITECTURE, and in the pending patent application Ser. No. 10/215,676 filed on Aug. 10, 2002, entitled BIT LINE SHARING AND WORLD LINE LOAD REDUCTION FOR LOW AC POWER SRAM ARCHITECTURE the SRAM architecture can be further modified to decrease power consumption by providing for word line and bit line sharing and by providing for sector selection where sections of the columns of memory cells can be selected for reading and writing. Both the LOW AC POWER STATIC RAM ARCHITECTURE application and the BIT LINE SHARING AND WORLD LINE LOAD REDUCTION FOR LOW AC POWER SRAM ARCHITECTURE application referred to above are hereby incorporated by reference in their entirety.
The invention herein provides further designs which further decrease the power consumption of the SRAM.
The present invention is directed to a static RAM system which allows for significant reduction in power consumption over prior systems by providing for partitioning columns of bit cells. One embodiment includes a plurality of columns of bit cells, wherein the columns of bit cells are partitioned into a plurality of sectors of bit cells. This embodiment provides a number of sector select circuits, where local bit lines couple sectors of bit cells with sector select circuits. The embodiment also provides a number of global bit lines which are coupled to the sector select circuits. The sector select circuits include a switch which couples the local bit line with the global bit line so that a selected bit cell in the sector of bit cells can be read from, or written to.
Another embodiment provides a sector select circuit for use in a SRAM system having a plurality of local bit lines and a plurality of global bit lines. The sector select circuit includes a mux circuit for coupling a local bit line of the SRAM with a global bit line of the SRAM system, and a first input for receiving a column select signal form the SRAM system. The sector select circuit also includes a second input for receiving a sector select signal from the SRAM system, and a local column select signal generation circuit which generates a local column select signal in response to receiving a sector select signal and column select signal. The mux circuit is coupled to the local column select signal circuit, and in response to a local column select signal, the mux couples the local bit with the with the global bit line.
Another embodiment provides a SRAM system having an array of bit cells including columns and rows of bit cells, wherein the columns of bit cells are partitioned into sectors of bit cells, and form an array of columns and rows of sectors of bits cells. Bit cells of the sectors of bit cells are coupled to a local bit line. An array of sector selection circuits including columns and rows of sector selection circuits are coupled to the sectors of bit cells, wherein a sector selection circuit is coupled to the local bit line coupled to bit cells of the sector of bit cells. The system also provides for column select lines which are coupled to a column of sector selection circuits, and sector selection lines, which are coupled rows of sector selection circuits. The system also provides global bit lines coupled to the column of sector selection circuits. The sector selection circuits include a first circuit and a switch, wherein the first circuit detects when a sector selection signal is present on the sector selection line and when a column selection signal is present on the column selection line and when both signals are present closes the switch whereby a local bit line to be coupled with a global bit line.
The features and advantages of the present invention will be more fully appreciated upon consideration of the following detailed description of the invention and the accompanying drawings, which set forth an illustrative embodiment in which the principles of the invention are utilized.